1. Field of the Invention
This invention relates generally to network processor-based devices, and more specifically to an improved system and method for reducing the complexity of resource identifier distribution in a large network processor-based system.
2. Discussion of the Prior Art
In today""s networked world, bandwidth is a critical resource. Increasing network traffic, driven by the Internet and other emerging applications, is straining the capacity of network infrastructures. To keep pace, organizations are looking for better technologies and methodologies to support and manage traffic growth and the convergence of voice with data.
The convergence of voice and data will play a large role in defining tomorrow""s network environment. Currently, the transmission of data over Internet protocol (IP) networks is free. Because voice communications will naturally follow the path of lowest cost, voice will inevitably converge with data. Technologies such as Voice over IP (VoIP), Voice over ATM (VoATM), and Voice over Frame Relay (VoFR) are cost-effective alternatives in this changing market. However, to make migration to these technologies possible, the industry has to ensure quality of service (QoS) for voice and determine how to charge for voice transfer over data lines.
Integrating legacy systems is also a crucial concern for organizations as new products and capabilities become available. To preserve their investments in existing equipment and software, organizations demand solutions that allow them to migrate to new technologies without disrupting their current operations.
Eliminating network bottlenecks continues to be a top priority for service providers. Routers are often the source of these bottlenecks. However, network congestion in general is often misdiagnosed as a bandwidth problem and is addressed by seeking higher-bandwidth solutions. Today, manufacturers are recognizing this difficulty. They are turning to network processor technologies to manage bandwidth resources more efficiently and to provide the advanced data services, at wire speed, that are commonly found in routers and network application servers. These services include load balancing, QoS, gateways, fire walls, security, and web caching.
For remote access applications, performance, bandwidth-on-demand, security, and authentication rank as top priorities. The demand for integration of QoS and CoS, integrated voice handling, and more sophisticated security solutions will also shape the designs of future remote access network switches. Further, remote access will have to accommodate an increasing number of physical mediums, such as ISDN, T1, E1, OC-3 through OC-48, cable, and xDSL modems.
A network processor (herein also mentioned as an xe2x80x9cNPxe2x80x9d) has been defined as a programmable communications integrated circuit capable of performing one or more of the following functions:
Packet classificationxe2x80x94identifying a packet based on known characteristics, such as address or protocol;
Packet modificationxe2x80x94modifying the packet to comply with IP, ATM, or other protocols (for example, updating the time-to-live field in the header for IP);
Queue/policy managementxe2x80x94reflects the design strategy for packet queuing, de-queuing, and scheduling of packets for specific applications; and,
Packet forwardingxe2x80x94transmission and receipt of data over the switch fabric and forwarding or routing the packet to the appropriate address.
For exemplary purposes, reference is made to FIG. 1 which illustrates a logical model of a generic Network Processor system 10. As shown in FIG. 1, multiple Network Processors (NP) 12 are shown connected using a switch fabric 15, with each of the network processors supporting a large number of external LAN or WAN interface ports 20. A separate General Purpose Processor (GPP) functions as a control point (CP) 25 for the system and has a physical or logical association with all of the Network Processors 12 in the system for enabling the customization and configuration of the Network Processor (NP) devices so that they may handle the forwarding of data packets and frames. It should be understood however, that the GPP may be embedded in a network processor device itself. The generic network processor system 10 comprises two major software components: 1) the control point code base running on the GPP, and, the programmable hardware-assist processors"" picocode in each of the network processors. These two software components are responsible for initializing the system, maintaining the forwarding paths, and managing the system. From a software view, the system is distributed. The GPP and each picoprocessor run in parallel, with the CP communicating with each picoprocessor using a predefined application program interface (API) 30 and control protocol.
The CP code base provides support for the Layer 2 and Layer 3 topology protocols and Layer 4 and Layer 5 network applications and systems management. Examples are protocol support for VLAN, IP, Multiprotocol Label Switching standard (MPLS) and equal-cost multipath (ECMP), and the supporting address- and route-learning algorithms to maintain topology information.
With particular reference to FIG. 1, and accompanying description found in commonly-owned, co-pending U.S. patent application Ser. No. 09/384,691 filed Aug. 27, 1999 and entitled xe2x80x9cNETWORK PROCESSOR PROCESSING COMPLEX AND METHODSxe2x80x9d, the whole contents and disclosure of which is incorporated by reference as if fully set forth herein, the general flow of a packet or frame received at the NP device is as follows: frames received from an network connection, e.g., Ethernet MAC, are placed in internal data store buffers by an upside xe2x80x9cenqueuexe2x80x9d device (EDS-UP) where they are identified as either normal data frames or system control frames (Guided Frames). In the context of the invention, frames identified as normal data frames are enqueued to an Embedded Processor Complex (EPC) which comprises a plurality of picoprocessors, e.g., protocol processors. These picoprocessors execute logic (picocode) capable of looking at the received frame header and deciding what to do with the frame (forward, modify, filter, etc.). The EPC has access to several lookup tables, and classification hardware assists to allow the picoprocessors to keep up with the high-bandwidth requirements of the Network Processor. A classification hardware assist device in particular, is provided for classifying frames of well known frame formats. The Embedded Processing Complex (EPC) particularly provides and controls the programmability of the NP device and includes, among other components (such as memory, dispatcher, interfaces), N processing units, referred to as GxH, which concurrently execute picocode that is stored in a common instruction memory. It is understood, however, that the architecture and structure is completely scalable towards more GxHs with the only limitation being the amount of silicon area provided in the chip. In operation, classification results from the classification hardware assist device are passed to the GxH, during frame dispatch. Each GxH preferably includes a Processing Unit core (CLP) which comprises, e.g., a 3-stage pipeline, general purpose registers and an ALU. Several GxHs in particular, are defined as General Data Handlers (GDH) each of which comprise a full CLP with the five coprocessors and are primarily used for forwarding frames. One GxH coprocessor, in particular, a Tree Search Engine Coprocessor (TSE) functions to access all tables, counters, and other data in a control memory that are needed by the picocode in performing tree searches used in forwarding data packets, thus freeing a protocol processor to continue execution. The TSE is particularly implemented for storing and retrieving information in various processing contexts, e.g., determining frame handling rules for routing, QoS treatment, lookup of frame forwarding information and, in some cases, frame alteration information.
Traditional frame routing capability provided in network processor devices typically utilize a network routing table having entries which provide a single next hop for each table entry. As known, in current Internet (network) packet routing protocols there may be implemented Internet Protocol (IP) Differentiated Services (DiffServ) which define a type of packet communication service. The Internet Engineering Task Force (IETF) standards that define these service may be found in the following references: a) An Architecture for Differentiated Services (RFC2475); b) An Expedited Forwarding PHB (RFC2598); and c) Assured Forwarding PHB Group (RFC2597) and, on-line, at http://www.ietf.org/html.charters/diffserv-charter.html. For example, Best Effort (BE) is the best-effort class of service such as what is generally available in the Internet today whereby all traffic flows get the same default treatment; the Expedited Forwarding (FE) is expedited forwarding, which is a premium class-of-service with strict QoS guarantees on latency and jitter, etc. There is no fixed set of DiffServ classes, however, the class-of-service information is conveyed in each packet header by encoding the DiffServ Code Point DSCP which is six (6) bits for defining up to 64 classes. The meaning of each class is defined by the service provider. There are recommended values for certain classes of service for interoperability, for example, BE, EF and Assured Forwarding (AF) have recommended encoding values.
Currently, in an example system with 64 NP devices that implements IP Differentiated Services (DiffServ) with each NP supporting 40 fast Ethernet ports, for example, in order to support the standard DiffServ service classes, at least six flow queues corresponding to six classes-of-service need to be defined on each port. This requires a total of about 64xc3x9740xc3x976 (i.e., 15,360) queue identifiers (QIDs) that need to be specified in the packet forwarding data structures which adds to the complexity of the system. It is understood that, a xe2x80x9cqueuexe2x80x9d may be associated with a xe2x80x9cflowxe2x80x9d which may be a port, or a neighboring device in case the port is connected to a shared medium such as an Ethernet LAN or a (MultiProtocol Label Switching) MPLS network tunnel, etc.
Considering an IP router 50 implemented with four Network Processors (NP) 12a-12d as shown in FIG. 2, and assuming that each NP device supports four OC-48 interfaces for a total of 16 ports on the router, in order to support IP Differentiated Services with say four classes-of-service per port, the networking software running on the Control Point (CP) 25 must create four queues on each port so that each queue is dedicated to a class-of-service. This results in a total of 16*4=64 queues on the router each identified via a queue identifier (queue control memory block memory address). Normally, these QIDs need to be distributed to every NP device so that packets can be routed to the appropriate queue. The distribution of such large number of queue identifiers among the NPs adds to the overhead of control traffic within the router device.
It would thus be highly desirable to provide a system and method that overcomes the scalability problem by obviating the need to distribute queue id information to every source NP in a large distributed NP system (router).
It would thus be highly desirable to provide a system and method that overcomes the scalability problem by enabling the specification of mechanisms that enable an application to manage queues in smaller block increments, e.g., units of six.
It would thus be highly desirable to provide a system and method that enables routing decisions to be made by egress network processor devices that provide the interface ports via which packets having class service definitions are communicated.
Accordingly, it is an object of the present invention to provide in a network processing (NP) system implementing a plurality of NP devices, with each NP device including a plurality of interface ports, each port having associated one or more queues associated therewith, and wherein the NP system is enabled to provide IP Differentiated Service classes pertaining to packets to be communicated, a system and mechanism that overcomes the scalability problem by enabling an application to manage queues associated with ports of in smaller block increments.
It is a further object of the present invention to provide in a network processing (NP) system providing IP Differentiated Service classes pertaining to packets to be communicated, a system and mechanism for enabling an application to manage queues associated with interface ports of NP devices in blocks of six.
It is another object of the present invention to provide in a network processing (NP) environment, a system and method that enables queuing decisions to be made by egress network processor devices that provide the interface ports via which packets communicated in accordance with class service definitions are communicated. According to the principles of the invention, there is provided a router and routing methodology, wherein the router comprises one or more network processing (NP) devices for routing data packets from a source NP device to a destination device via a switch fabric, with each network processing device supporting a number of interface ports, each port capable of interfacing with one or more data queues for receiving packets associated with a class-of-service characterizing the forwarding treatment of the packets. The routing methodology comprises: classifying a packet to be forwarded from a source NP device according to a particular class-of-service and determining outgoing interface port information of a destination NP device to forward the packet, the interface port having a pre-defined queue base address associated therewith; encoding a queue index offset for the packet associated with a particular class-of-service associated with the packet to be routed; forwarding the packet, queue index offset and outgoing interface port information to the destination NP; and, determining a queue identifier from the base address and transmitted queue index offset for indicating a particular queue by which the classified packet is to be forwarded.
Advantageously, the queue identifier is determined locally at the destination NP device forwarding the packet, thus obviating the need for queue identifiers to be distributed throughout the network for packet routing purposes.